1. Field of the Invention
The present invention relates to a non-volatile random access memory and a fabrication method thereof and, more particularly, to a high-density non-volatile random access memory using a ferroelectric film as a capacitor insulation film and a fabrication method thereof.
2. Description of Related Arts
Typical randomly accessible memory devices include an SRAM (static random access memory) and DRAM (dynamic random access memory), which are both volatile memories. The former requires six transistors for one memory cell, thereby imposing a limitation on higher integration. The later suffers from an increased power consumption because capacitors thereof require periodical refreshing for data retention.
Recently, FRAMs (ferroelectric random access memories) employing a ferroelectric film as a capacitor dielectric film thereof have been attracting increasing attention. To reduce an area occupied by memory cells, a stacked memory cell structure is realized in some of the FRAMs, which structure is often employed in DRAMs.
Such stacked FRAM cells are proposed, for example, in Japanese Unexamined Patent Publications No. 3-296262 (1991) and No. 4-356958 (1992).
FIG. 12 illustrates one exemplary memory cell of the stacked FRAMs in accordance with the aforesaid publications. The memory cell comprises an MOS transistor having a gate electrode 43 formed on a semiconductor substrate 41 with intervention of a gate insulation film 42 and a pair of source/drain regions 44, a ferroelectric capacitor having a bottom electrode 49 connected to one of the source/drain regions 44 of the MOS transistor via a contact plug 45, a PZT ferroelectric film 50 fully covering the bottom electrode 49 and a top electrode 51 fully covering the ferroelectric film 50. The other source/drain region 44 of the MOS transistor is connected to a bit line 48, and a BPSG film and SiO.sub.2 film are formed as interlayer insulation films 46 and 47 on the MOS transistor and the ferroelectric capacitor, respectively. A drive line 52 extending perpendicular to the extension direction of the gate electrode 43 is connected to the top electrode 51 of the ferroelectric capacitor.
FIG. 13 illustrates memory cell of a stacked FRAM of another type. The memory cell has substantially the same construction as that shown in FIG. 12, except that the edges of the bottom electrode 53, ferroelectric film 54 and top electrode 55 of the ferroelectric capacitor are aligned.
In the memory cell shown in FIG. 13, however, it is difficult to control etching of the three-layered films 53, 54 and 55 which comprises the capacitor. Also it is not possible to form the top electrode 55 in an desired shape, so that it is necessary to form a separate drive line.
In the memory cell of the FRAM shown in FIG. 12, since the top electrode 51 fully covers the ferroelectric film 50 which covers the bottom electrode 49, the side portions of the ferroelectric film 50 do not directly contact the SiO.sub.2 film 47. However, since the ferroelectric film 50 is formed to be in contact with the interlayer insulation film 46, an interdiffusion occurs between the interlayer insulation film 46 and the ferroelectric film 50 in an annealing process for crystallization, resulting in peeling-off of the ferroelectric film. Moreover, additional photolithographic and etching processes are required for the patterning of the ferroelectric film 50 and the top electrode 51. Further, the ferroelectric film 50 may be contaminated or damaged in the photolithographic and etching processes. Therefore, it is preferred that the ferroelectric film 50 be etched together with a top electrode material after the top electrode material is deposited on the ferroelectric film 50. In FIG. 13 also, the side surface of the ferroelectric film 54 comes in contact with the interlayer insulation film 47, so that an interdiffusion might possibly occur during the formation of the interlayer insulation film 47. However, since the temperature for forming the interlayer insulation film is lower than the temperature for crystallization of the ferroelectric film, the degree of interdiffusion is lower in the case of FIG. 13 than in the case of FIG. 12.
In a still another prior art, the top electrode 51 or 55 of the ferroelectric capacitor is provided as a common plate electrode for memory cells. However, when a predetermined voltage is applied to the top electrode 51 or 55 to rewrite or read out data, memory cells surrounding the selected memory cell are liable to be disturbed.